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Mizar Web>MathematicsSubjectClassification>94>94C>94C99 (2006-11-24, MarcoRiccardi)EditAttach
Mizar Web>MathematicsSubjectClassification>94>94C>94C99 (2006-11-24, MarcoRiccardi)EditAttach94C99 Circuits, networks - None of the above, but in this section
Primary classification
| # | Article | ||
|---|---|---|---|
| 1 | gate_1 | Logic Gates and Logical Equivalence of Adders | Yatsuka Nakamura |
| 2 | gate_2 | Correctness of Binary Counter Circuits | Yuguang Yang , Wasaki Katsumi , Yasushi Fuwa and Yatsuka Nakamura |
| 3 | gate_3 | Correctness of Johnson Counter Circuits | Yuguang Yang , Wasaki Katsumi , Yasushi Fuwa and Yatsuka Nakamura |
| 4 | gate_4 | Correctness of a Cyclic Redundancy Check Code Generator | Yuguang Yang , Katsumi Wasaki , Yasushi Fuwa and Yatsuka Nakamura |
| 5 | gate_5 | Correctness of the High Speed Array Multiplier Circuits | Hiroshi Yamazaki and Katsumi Wasaki |
Secondary classification
| # | Article | ||
|---|---|---|---|
| WebForm | |
|---|---|
| TopicClassification | MathSC2000 |
| ProjectGroup? | |
| ImplementationDate? | N/A |
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Topic revision: r1 - 2006-11-24 - 17:37:47 - MarcoRiccardi
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